The present invention relates to the design of integrated circuits or systems on a chip, and more particularly to a method for designing and optimizing a desired algorithm to facilitate optimum chip design.
The rapidly growing gap between silicon capacity and design productivity has resulted in a pressing need for design reuse. Hardware building blocks, usually under the name of cores, have become increasingly popular as the most efficient way of reusing design intellectual property (IP). While there exist several potential classification schemes for integrated circuits (IC) IP, the classification of cores according to their level of implementation details is by far the most popular. Currently, hardware intellectual property (IP) is delivered at three levels of abstraction: hard, firm, and soft.
Hard cores are completely implemented using a particular physical design library. Firm cores are also completely implemented, including physical design, but are targeted at a symbolic library. Finally, soft cores are described in high level languages such as VHDL or Verilog. Clearly, while hard cores provide complete information about all relevant design parameters and facilitate the highest level of performance and implementation parameter optimization for the selected library, soft cores are superior in terms of their flexibility and application range. Initially, hard cores dominated the design reuse market and practice, but recently there is an increasing trend toward other types of cores and in particular, soft cores. Additionally, parameterized, configurable, and programmable cores (such as Tensilica and Improv) have been rapidly gaining popularity.
In general, the hard cores require the most time and effort to design, but use the smallest silicon area. Soft cores can be designed most quickly, but require the largest silicon area. The firm core designs are somewhere between the hard and soft designs in terms of both the design expense and the amount of silicon required for the physical implementation.
For all types of cores, whether hard, firm or soft, the basic techniques for implementing a desired algorithm are well known. A customer will normally specify an application and a desired algorithm. The core design team starts with the selected algorithm and implements the application on a chip using one of the known approaches. Typically, the hard core approach may be selected if the application will require a large number of chips and/or if the application is expected to be used for a long period of time. If the projected number of chips is small and/or the application is expected to be useful for only a short period of time, it is probably best to implement the application on a soft core. The firm design approach falls between the hard and soft.